AD9695BCPZ-1300   AD9695BCPZ-625

The AD9695 is a dual, 14-bit,  1300 MSPS/625 MSPS analog-todigital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.

The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin.

The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. This product may be protected by one or more U.S. or international patents.

Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.

Product Highlights

1. Low power consumption per channel.

2. JESD204B lane rate support up to 16 Gbps.

3. Wide, full power bandwidth supports intermediate

• Buffered inputs ease filter design and implementation.

• Four integrated wideband decimation filters and NCO

• Programmable fast overrange detection.

• On-chip temperature diode for system thermal management.

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Applications

• Communications

• Diversity multiband, multimode digital receivers

  • 3G/4G, TD-SCDMA, WCDMA, GSM, LTE

  
  

• General-purpose software radios

• Ultrawideband satellite receiver

• Instrumentation

  • Oscilloscopes

  • Spectrum analyzers

  • Network analyzers

  • Integrated RF test solutions

  
  

• Radar

• Electronic support measures, electronic counter measures, and electronic counter-counter measures

• High speed data acquisition systems

• DOCSIS 3.0 CMTS upstream receive paths

• Hybrid fiber coaxial digital reverse path receivers

• Wideband digital predistortion